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Title: Assistance in Hierarchical and Structured Design 
       Using Temporal Logic and Prolog

 Masahiro FUJITA **
 Shinji KONO *
 Hidehiko TANAKA *
 Tohru MOTO-OKA *

 * : Univerisity of Tokyo
 **: Fujitsu Laboratory Ltd.

1. Introduction (3)
  Assistance in Hierarchical and Structured Design 

2. Temporal Logic and Hardware Specification (4)
  LTTL and Timing Diagram Descriptions
  Parallel and Sequential -> Chop -> interval name

3. Tempura: Temporal Logic as a Programming Language (6)
  ITL and LTTL and Tempura
  How to Hierarchical Design in Tempura 

4. Interpreter (4)
  Way of Execution and Sample Run

5. Hardware Description in Prolog
  How to describe hardware in Prolog

6. Synthesis of State Diagram (4)
  Temporal Operator Expansion Rules

7. Verification of Synchronization Parts (5)
  Gate, Stae Diagram and Temporal Logic

8. Conclusions (2)
  Future Research Topics

References (2)
